- The 18th Annual ACM SIGPLAN / SIGBED Conference on Languages, Compilers, and Tools for Embedded SystemsLCTES 2017

Static program analysis is increasingly recognized as a fundamental tool for compiler optimization, bug detection and security analysis (among others). Pointer analysis is the foundation, on which virtually all other analyses are based. In this talk, I will introduce a number of pointer analysis techniques developed in my research group, together with their applications for improving software performance, safety and security. I will conclude my talk by discussing some challenges and opportunities faced in developing practical pointer analyses for real-world applications.

Jingling Xue

UNSW Australia

Jingling Xue received his BSc and MSc degrees in Computer Science and Engineering from Tsinghua University in 1984 and 1987, respectively, and his PhD degree in Computer Science and Engineering from Edinburgh University in 1992. He is currently a Scientia Professor in the School of Computer Science and Engineering, University of New South Wales, Australia, where he leads the Programming Languages and Compilers Group.

Jingling Xue’s main research interest has been programming languages and compilers for over 25 years. He is currently supervising a group of postdocs and PhD students on a number of topics including programming and compiler techniques for multi-core processors and embedded systems, concurrent programming models, static and dynamic program analysis for bugs and security vulnerabilities, security analysis of Android apps, and automatic parallelization of programs for parallel and distributed systems. His research has been supported by Intel, Sun Microsystems, Oracle, Huawei and Australian Research Council.

Jingling Xue is interested in sharing the outcomes of his research projects in the form of open-source tools (http://www.cse.unsw.edu.au/~jingling/tools.html).

Jingling Xue is an Associate Editor for several journals, including IEEE Transactions on Computers (2011 – 2015), Software: Practice and Experience, and Journal of Computer Science and Technology. He has served as a program committee member in numerous conferences in his field.

Just-in-time (JIT) compilation during program execution and ahead-of-time (AOT) compilation during software installation are alternate techniques used by managed language virtual machines (VM) to generate optimized native code while simultaneously achieving binary code portability and high execution performance. Profile data collected by JIT compilers at run-time can enable profile-guided optimizations (PGO) to customize the generated native code to different program inputs. AOT compilation removes the speed and energy overhead of online profile collection and dynamic compilation, but may not be able to achieve the quality and performance of customized native code. The goal of this work is to investigate and quantify the implications of the AOT compilation model on the quality of the generated native code for current VMs.

First, we quantify the quality of native code generated by the two compilation models for a state-of-the-art (HotSpot) Java VM. Second, we determine how the amount of profile data collected affects the quality of generated code. Third, we develop a mechanism to determine the accuracy or similarity for different profile data for a given program run, and investigate how the accuracy of profile data affects its ability to effectively guide PGOs. Finally, we categorize the profile data types in our VM and explore the contribution of each such category to performance.

April W. Wade

University of Kansas

Prasad Kulkarni

University of Kansas

Michael Jantz

University of Tennessee

Heterogeneous multi-core architectures consisting of CPUs and GPUs are commonplace in today’s embedded systems. These architectures offer potential for energy efficient computing if the application task is mapped to the right core. Realizing such potential is challenging due to the complex and evolving natural of hardware and applications. This paper presents an automatic approach to map OpenCL kernels onto heterogeneous multi-cores for a given optimization criterion – whether it is faster runtime, lower energy consumption or a trade-off between them. This is achieved by developing a machine learning based approach to predict which processor to use to run the OpenCL kernel and the host program, and at what frequency the processor should operate. Instead of hand-tuning a model for each optimization metric, we use machine learning to develop a unified framework that first automatically learns the optimization heuristic for each metric off-line, and then uses the learned knowledge to schedule OpenCL kernels at runtime based on code and runtime information of the program. We apply our approach to a set of representative \OpenCL benchmarks and evaluate it on an ARM big.LITTLE mobile platform. Our approach achieves over 93% of the performance delivered by an oracle predictor. We obtain, on average, 1.2x, 1.6x, and 1.8x improvement respectively for runtime, energy consumption and the energy delay product, when compared to a state-of-the-art heterogeneous-aware OpenCL task mapping scheme.

Ben Taylor

Lancaster University, UK

United Kingdom

Vicent Sanz Marco

Lancaster University

Zheng Wang

Lancaster University

The parallelization of programs and distributing their workloads to multiple threads can be a challenging task. In addition to multi- threading, harnessing vector units in CPUs proves highly desirable. However, employing vector units to speed up programs can be quite tedious. Either a program developer solely relies on the auto-vectorization capabilities of the compiler or he manually applies vector intrinsics, which is extremely error-prone, difficult to maintain, and not portable at all. Based on whole-function vectorization, a method to replace con- trol flow with data flow, we propose auto-vectorization techniques for image processing DSLs in the context of source-to-source com- pilation. The approach does not require the input to be available in SSA form. Moreover, we formulate constraints under which the vectorization analysis and code transformations may be greatly sim- plified in the context of image processing DSLs. As part of our methodology, we present control flow to data flow transformation as a source-to-source translation. Moreover, we propose a method to efficiently analyze algorithms with mixed bit-width data types to determine the optimal SIMD width, independently of the target instruction set. The techniques are integrated into an open source DSL framework. Subsequently, the vectorization capabilities are compared to a variety of existing state-of-the-art C/C ++ compilers. Speedups of up to 7.4 are observed for benchmarks taken from ISPC and image processing, compared to non-vectorized executions.

Oliver Reiche

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)

Germany

Christof Kobylko

Frank Hannig

Friedrich-Alexander University Erlangen-Nürnberg (FAU)

Germany

Jürgen Teich

More and more modern processors have been supporting non-contiguous SIMD data accesses. However, translating such instructions has been overlooked in the Dynamic Binary Translation (DBT) area. For example, in the popular QEMU dynamic binary translator, guest memory instructions with strides are emulated by a sequence of scalar instructions, leaving a significant room for performance improvement when the host machines have SIMD instructions available. Structured loads/stores, such as VLDn/VSTn in ARM NEON, are one type of strided SIMD data access instructions. They are widely used in signal processing, multimedia, mathematical and 2D matrix transposition applications. Efficient translation of such structured loads/stores is a critical issue when migrating ARM executables to other ISAs. However, it is quite challenging since not only the translation of structured loads/stores is not trivial, but also the difference between guest and host register configurations must be taken into consideration. In this work, we present the design and implementation of translating structured loads/stores in DBT, including target code generation as well as efficient SIMD register mapping. Our proposed register mapping mechanisms are not limited to handling structured load/stores, they can be extended to deal with normal SIMD instructions. On a set of OpenCV benchmarks, our QEMU-based system has achieved a maximum speedup of 5.41x, with an average improvement of 2.93x. On a set of BLAS benchmarks, our system has also obtained a maximum speedup of 2.19x and an average improvement of 1.63x.

Sheng-Yu Fu

Ding-Yong Hong

Institute of Information Science, Academia Sinica

Ping Yu

Department of Computer Science and Information Engineering, National Taiwan University

Jan-Jan Wu

Institute of Information Science, Academia Sinica

Wei-Chung Hsu

Dept. Computer Science & Information Engineering, National Taiwan University

Pipelined heterogeneous multiprocessor system-on-chip (MPSoC) can provide high throughput for streaming applications. In the design of such systems, time performance and system cost are the most concerning issues. By analyzing runtime behaviors of benchmarks in real-world platforms, we find that execution times of tasks are not fixed but spread with probabilities. In terms of this feature, we model execution times of tasks as random variables. In this paper, we study how to design high-performance and low-cost MPSoC systems to execute a set of such tasks with data dependencies in a pipelined fashion. Our objective is to obtain the optimal functional unit assignment and voltage selection for the pipelined MPSoC systems, such that the system cost is minimized while timing constraints can be met with a given guaranteed probability. For each required probability, our proposed algorithm can efficiently obtain the optimal solution. Experiments show that other existing algorithms cannot find feasible solutions in most cases, but ours can. Even for those solutions that other algorithms can obtain, ours can reach 30% reductions in total cost compared with others.

Weiwen Jiang

Chongqing University

Edwin Sha

Chongqing University

Qingfeng Zhuge

Chongqing University, China

Hailiang Dong

Chongqing University

Xianzhang Chen

Chongqing University

The explosion of networked devices has driven a new computing environment called the Internet of Things (IoT), enabling various services such as home automation and health monitoring. Despite the promising applicability of the IoT, developing an IoT service is challenging for programmers, because the programmers should integrate multiple programmable devices and heterogeneous third-party devices. Recent works have proposed integrated programming platforms, but they either require device-specific implementation for third-party devices without any device abstraction, or abstract all the devices to the standard interfaces requiring unnecessary abstraction of programmable devices. To integrate IoT devices with selective abstraction, this work revisits the object oriented programming (OOP) model, and proposes a new language extension and its compiler-runtime framework, called Esperanto. With three annotations that map each object to its corresponding IoT device, the Esperanto language allows programmers to integrate multiple programmable devices into one OOP program and to abstract similar third-party devices into their common ancestor classes. Given the annotations, the Esperanto compiler automatically partitions the integrated program into multiple sub-programs for each programmable IoT device, and inserts communication and synchronization code. Moreover, for the ancestor classes, the Esperanto runtime dynamically identifies connected third-party devices, and links their corresponding descendent objects. Compared to an existing approach on the integrated IoT programming, Esperanto requires 33.3% fewer lines of code to implement 5 IoT services, and reduces their response time by 44.8% on average.

Gyeongmin Lee

POSTECH

Seonyeong Heo

POSTECH

Bongjun Kim

POSTECH

Jong Kim

POSTECH

Hanjun Kim

POSTECH

MARTE (abbreviated for Modeling and Analysis of Real-Time and Embedded systems) is a UML profile, used to facilitate the design and analysis of real-time and embedded systems. The Clock Constraint Specification Language (CCSL) is a formal language companion to MARTE, which is proposed to specify the constraint of the occurrences of events in systems. However, the language lacks efficient verification support to the formal analysis of temporal properties which are important to real-time and embedded systems. In this paper, we propose an SMT-based approach to model checking of the temporal properties specified in Linear Temporal Logic (LTL) for CCSL. We implement a prototype tool for the proposed approach and use the state-of-the-art tool Z3 as the underlying SMT solver. We model two practical cases including a traffic light controller and a power window system in CCSL, and verify LTL properties of the two systems using the proposed approach. Experimental results demonstrate the effectiveness of our approach.

Min Zhang

East China Normal University

China

Yunhui Ying

Modern embedded processors provide hardware support for cache locking, a mechanism used to facilitate the WCET (Worst-Case Execution Time) calculation of a task. We investigate the problem of integrating task scheduling and cache locking for a set of pre-emptible tasks with individual release times and deadlines on a multicore processor with two level caches. We propose a novel integrated approach that schedules the task set and allocates the locked cache contents of each task to the local caches (L1 caches) and the level two cache (L2 cache). Our approach consists of three major components, the task scheduler, the L1 cache allocator, and the L2 cache allocator. The task scheduler aims at minimizing the number of task preemptions. The L1 cache allocator converts the interference graph of all the tasks scheduled on each core into a DAG by considering the preemptions between tasks and allocates L1 cache space to each task. The L2 cache allocator converts the interference graph of all the tasks into a DAG by using a k-longest-path based graph orientation algorithm and allocates L2 cache space to each task. Both cache allocators significantly improve the utilization of all the caches due to the efficient use of the interference graphs of tasks. We have implemented our approach and compared it with the extended version of the preemption tree-based approach and the static analysis approach without cache locking by using a set of benchmarks from the MRTC benchmark suite and SNU real-time benchmarks. Compared to the extended version of the preemption tree-based approach, the maximum WCRT (Worst Case Response Time) improvement of our approach is 15%. Compared to the static analysis approach, the maximum WCRT improvement of our approach is 37%.

Wenguang Zheng

Hui Wu

University of New South Wales, Australia

Chuanyao Nie

The University of New South Wales

Engineering systems software is considered difficult. Performance considerations often dominate the overall development process resulting in significant code complexity. In our experience, however, completely ignoring performance, at least originally, may result in valuable insight and sometimes even more rigorous development methodologies that may still enable high performance designs. We discuss three examples developed over a period of around fifteen years: (1) Giotto, a real-time programming language based on logical execution time (LET), (2) the Embedded Machine, a virtual machine making real-time code portable including compiled Giotto programs, and (3) Selfie, a fully self-contained system of a tiny self-compiling C compiler, a tiny self-executing MIPS emulator targeted by the compiler, and a tiny self-hosting hypervisor virtualizing the emulator. Giotto shows how being slow can be leveraged to avoid non-determinism in real-time code. The Embedded Machine is an interpreter that may be slow but nevertheless makes code portable that appeared to be intrinsically non-portable. Selfie, finally, reveals that an operating system is a simple interpreter until people wanted speed.

Christoph Kirsch

University of Salzburg

Austria

Christoph Kirsch is Professor at the Department of Computer Sciences of the University of Salzburg, Austria. He received his Dr.Ing. degree from Saarland University, Saarbrücken, Germany, in 1999 while at the Max Planck Institute for Computer Science. From 1999 to 2004 he worked as Postdoctoral Researcher at the Department of Electrical Engineering and Computer Sciences of the University of California, Berkeley. He later returned to Berkeley as Visiting Scholar (2008-2013) and Visiting Professor (2014) at the Department of Civil and Environmental Engineering as part of a collaborative research effort in Cyber-Physical Systems. His research interests are in concurrent programming, memory management, virtualization, and automated theorem proving. Dr. Kirsch co-invented embedded programming languages and systems such as Giotto, HTL, and the Embedded Machine, and more recently co-designed high-performance, multicore-scalable concurrent data structures and memory management systems. He co-founded the International Conference on Embedded Software (EMSOFT) and served as ACM SIGBED chair from 2011 until 2013 and ACM TODAES associate editor from 2011 until 2014. He is currently associate editor of IEEE TCAD.

Convolutional neural networks (CNNs) are widely adopted in artificial intelligent systems. In contrast to conventional computingcentric applications, the computational and memory resources of CNN applications are mixed together in the network weights. This incurs a significant amount of data movement, especially for highdimensional convolutions. Although recent embedded 3D-stacked Processing-in-Memory (PIM) architecture alleviates this memory bottleneck to provide fast near-data processing, memory is still a limiting factor of the entire system. An unsolved key challenge is how to efficiently allocate convolutions to 3D-stacked PIMto combine the advantages of both neural and computational processing.

This paper presents Memolution, a compiler-based memoryefficient data allocation strategy for convolutional neural networks on PIM architecture. Memolution offers thread-level parallelism that can fully exploit the computational power of PIMarchitecture. The objective is to capture the characteristics of neural network applications and present a hardware-independent design to transparently allocate CNN applications onto the underlining hardware resources provided by PIM. We demonstrate the viability of the proposed technique using a variety of realistic convolutional neural network applications. Our extensive evaluations show that, Memolution significantly improves performance and the cache utilization compared to the baseline scheme.

Yi Wang

Shenzhen University

Mingxu Zhang

Shenzhen University

Jing Yang

Harbin Institute of Technology

Software-Defined Networking (SDN) allows control applications to install fine-grained forwarding policies in the underlying switches. Ternary Content Addressable Memory (TCAM) enables fast lookups in hardware switches with flexible wildcard rule patterns. However, the performance of packet processing is severely constrained by the capacity of TCAM, aggravating the processing burden and latency issues. In this paper, we propose a hybrid TCAM architecture which consists of NVM-based TCAM (nvTCAM) and SRAM-based TCAM (sTCAM), utilizing nvTCAM to cache the most popular rules to improve cache-hit-ratio while relying on a very small-size sTCAM to handle cache-miss traffic to effectively decrease update latency. Considering the special rule dependency, we present a Rule Migration Replacement Algorithm to effectively make full utilization of both nvTCAM and sTCAM to obtain better performance. Experimental results show our proposed architecture outperforms current TCAM architectures.

Xianzhong Ding

Shandong University

Zhiyong Zhang

Shandong University

Zhiping Jia

Shandong University

Lei Ju

Shandong University

China

Mengying Zhao

Shandong University

Huawei Huang

The University of Aizu

Energy harvesting techniques become increasingly popular as power supplies for embedded systems. However, the harvested energy is intrinsically unstable. Thus, the program execution may be interrupted frequently. Although the development of non-volatile processors (NVP) can save and restore execution states, both hardware and software challenges exist for energy harvesting powered embedded systems. On the hardware side, existing power detector only signals the ``poor'' quality of the harvested power based on a preset threshold voltage. The inappropriate setting of this threshold will make the NVP system suffer from either unnecessary checkpointings or checkpointing failures. On the software side, not all tasks can be checkpointed. Once the power is off, these tasks will have to restart from the beginning. In this paper, a task scheduler is proposed to maximize task progress by prioritizing uncheckpointable tasks if power is weak so that they can finish before the power failure. To assist task scheduling, three additional modules including voltage monitor, checkpointing handler, and routine handler, are proposed. Experimental results show increased overall task progress and reduced energy consumption.

Chen Pan

Mimi Xie

Oklahoma State University

Yongpan Liu

Tsinghua University

Yanzhi Wang

Syracuse University

Jason Xue

City University of Hong Kong, China

Yiran Chen

University of Pittsburgh

Jingtong Hu

Oklahoma State University

The employment of a real-time operating system (RTOS) in an embedded control systems is often an all-or-nothing decision: While the RTOS-abstractions provide for easier software composition and development, the price in terms of event latencies and memory costs are high. Especially in HW/SW codesign settings, system developers try to avoid the employment of a full-blown RTOS as far as possible. In OSEK-V, we mitigate this trade-off by a very aggressive tailoring of the concrete RTOS instance into the hardware. Instead of implementing generic OS components as custom hardware devices, we capture the actually possible application–kernel interactions as a finite-state machine and integrate the tailored RTOS semantics directly into the processor pipeline. In our experimental results with an OSEK-based implementation of a quadrotor flight controller into the Rocket/RISC-V softcore, we thereby can significantly reduce event latencies, interrupt lock times, and memory footprint at moderate costs in terms of FPGA resources.

Christian Dietrich

Daniel Lohmann

Friedrich-Alexander-Universität, Germany

Dynamic Binary Modification (DBM) is a technique for modifying applications transparently while they are executed, working at the level of native code. However, DBM introduces a performance overhead, which in some cases can dominate execution time, making many uses impractical.

The ARM hardware ecosystem poses unique challenges for high performance DBM systems because of the large number and wide range of capabilities of the commercially available implementations: from single issue, in order cores up to 6-issue out-of-order cores and including less traditional implementations. These variations raise the question of whether it is possible to develop DBM optimisations which either improve or, at the very least, do not affect performance on all available systems and microarchitectures. To answer this question, the performance of three new optimisations for the MAMBO DBM system has been evaluated on three systems using different microarchitectures. For comparison, the overhead of DynamoRIO, a high performance DBM system which was recently ported to the ARM architecture, is also evaluated.

Cosmin Gorgovan

University of Manchester

Amanieu d'Antras

University of Manchester

Mikel Luján

University of Manchester

Real-time systems are shifting from single-core to multi-core processors. Software must be parallelized to fully utilize the computation power of multi-core architecture. OpenMP is a popular parallel programming framework in general and high-performance computing, and recently has drawn a lot of interests in embedded and real-time computing. Much recent work has been done on real-time scheduling of OpenMP-based parallel workload. However, these studies conduct evaluations with randomly generated task systems, which cannot well represent the structure features of OpenMP workload. This paper presents a benchmark suite, ompTGB, to support research on real-time scheduling of OpenMP-based parallel tasks. ompTGB does not only collect realistic OpenMP programs, but also models them into task graphs so that the real-time scheduling researchers can easily understand and use them. We also present a new response time bound for a subset of OpenMP programs and use it to demonstrate the usage of ompTGB.

Sun Jinghao

Nan Guan

Hong Kong Polytechnic University, China

Yang Wang

Northeastern University

Yang Wang

University of New Brunswick

Mingsong Lv

Northeastern University

Wang Yi

Uppsala University, Sweden

In this paper, we present a checkpointing-aware loop tiling method for energy harvesting powered non-volatile processors. As power failures of energy harvesting system happen naturally, checkpointing is needed during the program execution. We observe that checkpointing is implemented with high overhead in applications with loops. We are motivated to reduce the amount of checkpointing data by analyzing data locality and shortening data lifetime in loops. This paper proposes checkpointing-aware loop tiling techniques which target to reduce the checkpointing and recovering overheads for loops. First, we analyze the optimal tile size for the nest loops considering checkpointing distance. Then, checkpointing and recovery schemes for tiling loops are proposed. Finally, the experiments are implemented to evaluate the effectiveness. The experimental results show that compared to the most related work, the proposed method reduce the checkpointing and recovering overheads significantly.

Fuyang Li

Department of Computer Science, City University of Hong Kong, Hong Kong

Keni Qiu

Capital Normal University, Beijing, China

Qingan Li

State Key Laboratory of Software Engineering, Wuhan University, China

Mengying Zhao

Shandong University

Jingtong Hu

Oklahoma State University

Yongpan Liu

Tsinghua University

Jason Xue

City University of Hong Kong, China